World Library  
Flag as Inappropriate
Email this Article

Motorola 68020

Article Id: WHEBN0000020302
Reproduction Date:

Title: Motorola 68020  
Author: World Heritage Encyclopedia
Language: English
Subject: Amiga, Motorola 68030, DEMOS, Apollo/Domain, Motorola 68040
Collection: 68K Microprocessors
Publisher: World Heritage Encyclopedia

Motorola 68020

XC68020, a prototype of the 68020

The Motorola 68020 ("sixty-eight-oh-twenty", "sixty-eight-oh-two-oh" or "six-eight-oh-two-oh") is a 32-bit microprocessor from Motorola, released in 1984. It is the successor to the Motorola 68010 and is succeeded by the Motorola 68030. A lower cost version was also made available, known as the 68EC020. In keeping with naming practices common to Motorola designs, the 68020 is usually referred to as the '020, pronounced oh-two-oh or oh-twenty".


  • Description 1
    • Improvements over 68010 1.1
    • Coprocessor support 1.2
    • Multiprocessing features 1.3
    • Instruction set 1.4
    • Addressing modes 1.5
  • Usage 2
  • Variant 3
  • Technical data 4
  • Bibliography 5
  • References 6
  • External links 7


Motorola 68020

The 68020 had 32-bit internal and external data and address buses, compared to the early models with 16-bit data and 24-bit address buses. Newer packaging methods allowed the '020 to feature more external pins without the large size that the earlier dual in-line package method required. The 68EC020 lowered cost through a 24-bit address bus. The 68020 was produced at speeds ranging from 12 MHz to 33 MHz.

Motorola 68020 die shot

Improvements over 68010

The 68020 added many improvements over the 68010 including a 32-bit arithmetic logic unit (ALU), 32-bit external data and address buses, extra instructions and additional addressing modes. The 68020 (and 68030) had a proper three-stage pipeline. Though 68010 had a "loop mode", which sped loops through what was effectively a tiny instruction cache, it held only two short instructions and was thus little used. The 68020 replaced this with a proper instruction cache of 256 bytes, the first 68k series processor to feature true on-board cache memory.

The previous 68000 and 68010 processors could only access word (16-bit) and long word (32-bit) data in memory if it were word-aligned (located at an even address). The 68020 had no alignment restrictions on data access. Naturally, unaligned accesses were slower than aligned accesses because they required an extra memory access.

Coprocessor support

The 68020 has a coprocessor interface supporting up to eight coprocessors. The main CPU recognizes "F-line" instructions (with the four most significant opcode bits all one), and uses special bus cycles to interact with a coprocessor to execute these instructions. Two types of coprocessors were defined, the floating point unit (MC68881 or MC68882 FPU) and the paged memory management unit (MC68851 PMMU). Only one PMMU can be used with a CPU. In principle multiple FPUs could be used with a CPU, but it was not commonly done. The coprocessor interface is asynchronous, so it is possible to run the coprocessors at a different clock rate than the CPU.

Multiprocessing features

Multiprocessing support was implemented externally by the use of a RMC pin[1] to indicate an indivisible read-modify-write cycle in progress. All other processors had to hold off memory accesses until the cycle was complete.[2] Software support for multiprocessing included the TAS, CAS and CAS2 instructions.

In a multiprocessor system, coprocessors could not be shared between CPUs. To avoid problems with returns from coprocessor, bus error, and address error exceptions, it was generally necessary in a multiprocessor system for all CPUs to be the same model, and for all FPUs to be the same model as well.

Instruction set

The new instructions included some minor improvements and extensions to the supervisor state, several instructions for software management of a multiprocessing system (which were removed in the 68060), some support for high-level languages which did not get used much (and was removed from future 680x0 processors), bigger multiply (32×32→64 bits) and divide (64÷32→32 bits quotient and 32 bits remainder) instructions, and bit field manipulations.

While the 68000 had 'supervisor mode', it did not meet the Popek and Goldberg virtualization requirements due to the single instruction 'MOVE from SR' being unprivileged but sensitive. Under the 68010 and later, this was made privileged, to better support virtualization software.

Addressing modes

The new addressing modes added scaled indexing and another level of indirection to many of the pre-existing modes, and added quite a bit of flexibility to various indexing modes and operations. Though it was not intended, these new modes made the 68020 very suitable for page printing; most laser printers in the early '90s had a 68EC020 at their core.

The 68020 had a minimal 256 byte direct-mapped instruction cache, arranged as 64 four-byte entries. Although small, it still made a significant difference in the performance of many applications. The resulting decrease in bus traffic was particularly important in systems relying heavily on DMA.

bottom view of a Motorola XC68020


The 68020 was used in the Apple Macintosh II and Macintosh LC personal computers, as well as Sun 3 workstations, the Hewlett-Packard 8711 Series Network Analyzers and later members of the HP 9000/300 family and the Alpha Microsystems AM-2000. Also the 68020 was an alternative upgrade to the Sinclair QL computer's 68008 in the Super Gold Card interface by Miracle Systems.

The Amiga 2500 and A2500UX was shipped with the A2620 Accelerator using a 68020, a 68881 floating point unit and the 68851 Memory Management Unit. The 2500UX shipped with Amiga Unix, requiring an '020 or '030 processor.

It is also the processor used on board TGV trains to decode signalling information which is sent to the trains through the rails. It is further being used in the flight control and radar systems of the Eurofighter Typhoon combat aircraft.

The Nortel Networks DMS-100 telephone central office switch also used the 68020 as the first microprocessor of the SuperNode computing core.

For more information on the instructions and architecture see Motorola 68000.


Motorola MC68EC020.

The 68EC020 is a microprocessor from Motorola. It is a lower cost version of the Motorola 68020. The main difference between the two is that the 68EC020 only has a 24-bit address bus, rather than the 32-bit address bus of the full 68020, and thus is only able to address 16 MB of memory.

The Commodore Amiga 1200 computer and the Amiga CD32 games console used the cost-reduced 68EC020; the Namco System 22 and Taito F3 arcade boards have also used this processor. It also found use in laser printers. Apple used it in the LaserWriter IIɴᴛx. Kodak used it in the Ektaplus 7016PS, and Dataproducts used it in the LZR 1260.

Technical data

Formal name MC68020[3]
Work frequency 12.5 , 16.67 , 20 , 25 , 33 MHz (minimum 8 MHz, no on-chip clock generation)[3]
Voltage supply 5 V
Maximum power 1.75 W[3]
Production process HCMOS, 3/8" silicon piece[3]
Chip carrier PGA 169 (114 pins used) 34.16 x 34.16 mm[3](53 °C/W without heatsink)[4]
Address bus 32-bit (4 GB directly linear accessible)[3]
Data bus 32-bit
Instruction set 101 CISC instructions
Cache 256 byte ICache[3][4]
  • 7 for Address operations (32-bit)[3]
  • 8 for Data operations (32-bit)[3]
Handling Branches Branch Prediction:
  • Fixed branch prediction, branch-never-taken approach.[5]
Transistors ~190 000[3]
Performance 5.36 MIPS @ 33MHz[4]


This article is based on material taken from the Free On-line Dictionary of Computing prior to 1 November 2008 and incorporated under the "relicensing" terms of the GFDL, version 1.3 or later.


  1. ^ , Appendix A, page 84"MC68020 Signal Description". Retrieved 2010-01-17. 
  2. ^ "5.3.3 Read-Modify-Write Cycle". MC68020/MC68EC020 Microprocessors User's Manual UM Rev. 1.0. Freescale Semiconductor. 1995. 
  3. ^ a b c d e f g h i j Rafiquzzaman, M. (2005). Fundamentals of Digital Logic and Microcomputer Design. John Wiley & Sons. pp. 577–578.  
  4. ^ a b c - M68020UM/AD REV.2 Users manual
  5. ^ Dandamudi, S. P. (2004). Guide to RISC Processors. p. 29.  

External links

  • 68020 images and descriptions at
This article was sourced from Creative Commons Attribution-ShareAlike License; additional terms may apply. World Heritage Encyclopedia content is assembled from numerous content providers, Open Access Publishing, and in compliance with The Fair Access to Science and Technology Research Act (FASTR), Wikimedia Foundation, Inc., Public Library of Science, The Encyclopedia of Life, Open Book Publishers (OBP), PubMed, U.S. National Library of Medicine, National Center for Biotechnology Information, U.S. National Library of Medicine, National Institutes of Health (NIH), U.S. Department of Health & Human Services, and, which sources content from all federal, state, local, tribal, and territorial government publication portals (.gov, .mil, .edu). Funding for and content contributors is made possible from the U.S. Congress, E-Government Act of 2002.
Crowd sourced content that is contributed to World Heritage Encyclopedia is peer reviewed and edited by our editorial staff to ensure quality scholarly research articles.
By using this site, you agree to the Terms of Use and Privacy Policy. World Heritage Encyclopedia™ is a registered trademark of the World Public Library Association, a non-profit organization.

Copyright © World Library Foundation. All rights reserved. eBooks from World eBook Library are sponsored by the World Library Foundation,
a 501c(4) Member's Support Non-Profit Organization, and is NOT affiliated with any governmental agency or department.